##################################################################### # CALL FOR PARTICIPATION # IP Based SoC Design'2002 # International Workshop & Exhibition # October 30-31, 2002 - Grenoble, France # http://www.us.design-reuse.com/WORKSHOP/IP_design02.html ##################################################################### This event combines the 11th edition of the IFIP workshop "IP based SoC Design" and the exhibition "SoC For a Connected World" organized by CMP Media Inc. WORKSHOP ======== The areas of interest for the workshop are IP based system design, IP/SoC qualification, IP/SoC Prototyping, IP/SoC modelling, internet technologies for IP exchange and other related topics. More than 80 papers will be presented in 16 sessions on two parallel tracks during the two days, and 3 panels on hot topics such as "IP Business Models" and "Network on Chip" are organized. Online registration: http://www.us.design-reuse.com/WORKSHOP/register.html EXHIBITION ========== The exhibition will be organized by CMP Media, Inc. during the 2 days of the workshop. Book your space now by contacting Tony Hennie (tonyhennie@aol.com). See the list of exhibitors: http://www.us.design-reuse.com/WORKSHOP/floorplan.html WORKSHOP PROGRAM COMMITTEE MEMBERS ================================== * Technical Program Chair: - Helena Krupnova - STMicroelectronics, France (Helena.Krupnova@st.com) * Program Committee Members: - Prof. K. ASADA - Tokyo University, Japan - P. BLOUET - ST Microelectronics, France - P. BRICAUD - Synopsys, France - Prof. F. BRGLEZ - NC State University, USA - A. BRUENING - Sci-worx GmbH, Germany - P. DWORSKY - Synopsys, USA - J. HAASE - Edacentrum, Germany - G. MARTIN - Cadence, USA - H.N. NGUYEN - Bull, France - T. PFIRSCH - Alcatel, France - F. RENOUX - Dolphin Integration, France - M. ROBERT - Lirmm, France - Prof. W. ROSENSTIEL - FZI Karlsruhe University, Germany - G. SAUCIER - Design And Reuse, France - Dr. R. SEEPOLD - Forschungszentrum Informatik, Germany - R. SUAYA - Mentor Graphics, France - Prof. R. UBAR - Tallinn Technical University, Estonia - Prof. N. WEHN - University of Kaiserslautern , Germany - H. VAN DER WILDT - Sagantec, USA WORKSHOP PROGRAM ================ (Online Version : http://www.us.design-reuse.com/WORKSHOP/program.html) ##################################### DAY 1 : Wednesday October 30 ##################################### # 07.00-08.20 - Registration ########## ROOM A: ########## # 08.20-08.30 - Welcome # 08.30-10.00 - Keynote Talks * "IP Market Challenges: Today and the Next Generation" John Chilton, Synopsys (USA) * "IP Management in a Large Company" Thierry Pfirsch, Alcatel (France) * "IP Market Overview and Outlook" Jim Tully, Gartner Dataquest (UK) * "IP/SoC Market" Gabriele Saucier, D&R (France) # 10.00-10.15 - Coffee Break # 10.15-11.35 - Session 1A : Impact of Submicron Technologies Chair person : Roberto Suaya, Mentor Graphics (France) * "Meeting the challenges of 90nm SoC design" Tim Daniels, LSI Logic (UK) * "Meeting the Challenges of Embedded Memory Design in Very Deep Sub-micron Processes" Mark Hileeto, ATMOS Corp. (Canada) * "Infrastructure IP: Aiding SOC Yields" Yervant Zorian, Virage Logic Corp. (USA) * "Creating good IP for physical design" Paul Rodman, ReShape, Inc.(USA) # 11.35-13.00 - Session 2A : IP Management and Collaborative Design Chair person : Prof. R. Ubar, Tallinn Technical University (Estonia) * "Transaction-based waveform analysis for IP Selection" Jian Liu, Eugene Shragowitz, University of Minnesota (USA) * "IP Transfer: a mapping problem" Gabriele Saucier, Lassaad Ghanmi, Mourad Hamdoun, Design And Reuse (France); Thierry Pfirsch, Alcatel (France); Menno ten Have, Philips (Germany); Martin Radetzki, Peter Neumann, sci-worx (Germany) * "Collaboration Support in Design - What is the message from CSCW and Knowledge Co-Production?" Konrad Kloeckner, Fraunhofer Institute for Applied Information Technology (FHG-FIT) (Germany) * "IP Configuration Management with Abstract Parameterizations " Holger Lange, Martin Radetzki, sci-worx (Germany) # 13.00-14.00 - Lunch # 14.00-16.00 - Session 3A : IP/SoC Design Methodology Chair person : Ian Phillips, ARM (UK) * "IBM: Catching the wave - SoC Solutions for the Internet Appliance Market" Juergen Hisberg, IBM Technology Group (Switzerland) * "IP Modeling and Reuse for SoC Design Using Standard Bus" Imed Moussa and Thierry Roudier, TNI-Valiosys (France) * "Tuning Fork - A Tool For Optimizing Parallel Configurable Processors" Shay Gal-On, Steve Novack, Oz Levia, Improv Systems (USA) * "Synthesizable Full-Custom Analog IP" Navraj Nandra, Barcelona Design Inc. (USA) * "ParaGraph - Shrinking the Parameter Space of IP utilizing Parameter Domains" Vasco Jerinic, Dietmar Mueller, University of Technology Chemnitz (Germany) * "IP Design for Dynamically Reconfigurable SoCs" Tobias Oppold, Wolfgang Rosenstiel, University of Tuebingen (Germany) # 16.00-16.15 - Coffee Break # 16.15-17.15 - Session 4A : IP Business Models Chair person : Philip Dworsky, Synopsys (USA) * "Intellectual Property Reuse - A New Business Model" Ken Reid, Cadence Design Foundry (UK) * "Defining IP Mall Business Models and Processes for Taiwan-s National Si-Soft Project" Professor Charles V. Trappey, Professor Kuei Ann (Stella) Wen, National Chiao Tung University; Professor Amy C. Trappey, National Tsing Hua University; Rayon Hsu, Avectec.com, Inc. (Taiwan) * "Mapping Cryptographically Enforced Pay-Per-Use Licensing of FPGA Intellectual Property" Tom Kean, Algotronix (UK) # 17.15-18.30 - Panel 1 : IP Business Models Moderator : Philip Dworsky, Synopsys (USA) Panelists : * Thierry Pfirsch, Alcatel (France) * Jim Tully, Gartner Dataquest (UK) * Jordan Selburn, iSuppli (USA) * Peter Hirt, ST Microelectronics (France) ########## ROOM B: ########## # 10.15-11.35 - Session 1B : IP/SoC Design (Best Prize) Chair person : Tim Daniels, LSI Logic (UK) * "A powerful dual-mode IP core for 802.11a/b Wireless LAN" Michel Eftimakis, NewLogic Technologies AG (France) * "A Bluetooth radio in 0.18m CMOS" Paul van Zeijl, Ericsson Technology Licensing (Netherlands) * "Optimizing MPEG-4 Video Decode on SH-5" Antony Bowers and Benedict R. Gaster, SuperH (UK) * "Design of an ip for aG729 voice decoding circuit" F. Sayadi, M. Marzougui, M. Atri, , E. Casseau*, R. Tourki, E. Martin, Laboratoire d-EE- Facult des sciences de Monastir (Tunisie); Laboratoire L.E.S.T.E.R - Universit de Bretagne Sud (Lorien) # 11.35-13.00 - Session 2B : IP/SoC Design (Best Prize) (Continued) Chair person : Tim Daniels, LSI Logic (UK) * "Bluetooth Baseband IP in an ARM9 environment" Jeff Robertson, Ericsson Technology Licensing (Sweden) * "Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation" Chang Choo, Silicon DSP (USA) * "Efficient Free-to-Air DVB-T System Solution Supported by IP-Based SoC Designs" David McBrien, Imagination Technologies & Frontier Silicon (UK) * "An Efficient FFT co-module using SOC approach" Ali Ahmadinia, Shaahin Hessabi, Sharif University of Technology (Iran) # 13.00-14.00 - Lunch # 14.00-16.00 - Session 3B : Verification IP Chair person : Andrew Betts, Qualis Europe (France) * "Synthesisable Verification IP" David Murray, Duolog Technologies (Ireland) * "Maximizing Verification Productivity: eVC Reuse Methodology (eRM)" Andrey Shvartz, Verisity Design (France) * "Attacking the verification challenge in next generation product design" Richard Pugh, Synopsys (Northern Europe) Ltd; Neill Mullinger, Synopsys Inc (USA) * "Assertion Based Emulation Methodology" Steve Wang, Axis Systems (USA) * "The Open Core Protocol Domain Verification Component (DVC)" Janick Bergeron, Stephane Brefort, Andy Betts, Qualis Europe SARL (France) * "Authoring Assertion IP using OpenVera Assertion Language" Surrendra Dudani, Eduard Cerny, Synopsys, Inc. (USA) # 16.00-16.15 - Coffee Break # 16.15-17.35 - Session 4B: Design Forum Chair person : Frederic Renoux, Dolphin (France) * "Integration Of Large ASICs in a -Startup Mode-" Neel Das,Hemanshu Bhatnagar, Corrent Corp. (USA) * "Extensible Processors Cores: Bridging the gap between SOC design productivity and gate availability" Steven Leibson, Tensilica Inc. (USA) * "CASE STUDY - Hands-on lessons from a legacy RT-level ATAPI IP Reuse" Jin-Seok Hong, Goang-Seog Choi, Ki-Seon Cho, Ju-Seon Kim, Jum-Han Bae, Samsung Electronics (Korea) * "Top-down SoC Design Methodology" Emre Tuncer, Wolfgang Helftricht, Monterey Design Systems, Inc. (USA) # 17.35-18.35 - Session 5B : Interface Chair person : Drew Wingard, Sonics (USA) * "Atlantic: a high-performance datapath interface for SOPC Designs-" Robert Cottrell, Altera (UK) * "Solving SOC Shared Memory Resource Challenges" W. David Schwaderer, Sonics Inc. (USA) * "High Speed SerDes IP Integration Challenges" Morgan H. Monks, David Rodriguez, Mouli Subramanian, Standard Microsystems Corporation (USA) # 18.35-19.35 - Panel 2 : Network on Chip Moderator : Michel Robert, LIRMM, University of Montpellier (France) Panelists : * Richard Hersemeule, ST Microelectronics (France) * Franck Seigeneret, Texas Instruments (France) * Cyril Spasveski, Prosilog (France) * Drew Wingard, Sonics (USA) * James P. Venabe, Palmchip (USA) # 19.35 - Banquet ##################################### # DAY 2 : Thursday October 31 ##################################### ########## ROOM A: ########## # 08.00-09.40 - Session 6A : Hardware / Software Integration Chair person : Patrick Blouet, STMicroelectronics (France) * "Co-simulation and Communication Synthesis for Intellectual Properties IPs Based SOCs: Approach and Experimentation" M. Marzougui, M. Abid, A. Baganne and R. Tourki, Laboratoire d'Electronique et de Micro-Electronique, Facult des Sciences de Monastir (Tunisie) * "Adaptation of IP Cores for the POLIS HW-SW" Moises Serra, Jeli Ordeix, Universitat de Vic (Spain); Joaquin Saiz, Lluis Ribas, Jordi Carrabina, Universitat Autnoma de Barcelona (Spain) * "System-level Exploration of Queuing Management Schemes for Input Queue Packet Switches" Chen He, University of Texas at Austin (USA); Marcello Lajolo, NEC USA, C&C Research Labs (USA) * "Software Rich Chips" Paul McLellan, VAST Systems Technology (USA) * "Management of Software IPs" Lassaad Ghanmi, Design And Reuse (France); Patrick Blouet, ST Microelectronics (France) # 09.40-10.00 - Coffee Break # 10.00-11.40 - Session 7A : Platform Based Design and Embedded System Chair person : Grant Martin, Cadence (USA) * "Bump in the Wire - The Design and Test of an Ethernet Security Development Platform" Doug Chisholm, Tality Corp. (UK) * "Platform Based Design - Enabling fast SoC time to Market" Thomas Boudrot, IBM Technology Group (Switzerland) * "The role of sockets in platform based design: a case study of the OMAP platform" Pete Cumming, Franck Seigneret, Texas Instruments (France) * "IP-Reuse and Platform based designs" Ramesh Chandra, STMicroelectronics, Inc. (USA) * "The Configurable VLIW Processor As The Base For A Cost Effective SoC Platform" Victor Berman, Improv Systems (USA) # 11.40-13.00 - Panel 3 : Platform Based Design and Embedded System Moderator : Grant Martin, Cadence (USA) Panelists : * Victor Berman, Improv (USA) * Ramesh Chandra, ST Microelectronics (USA) * Andre Kuntz, Philips Sophia (France) * Chris Lennard, ARM (UK) * Paul McLellan, VAST (USA) * Frank Seigneret, TI Sophia (France) # 13.00-14.00 - Lunch # 14.00-15.00 - Session 9A : Far East Activities in IP Exchange and IP Based SoC Design Chair person : Prof. Kunihiro Asada, Tokyo University (Japan) * "IP Exchange Activities and IP Needs for Japanese Electronics Market" Motoaki Ito, Nobuyuki Miyazaki and Shojiro Mori, IPTC Corporation (Japan) * "Activities of SIPAC in IP/SoC industry of Korea" Shiho Kim, SIPAC (Korea) * "IP/SoC Project in Taiwan" Prof. Chen-Yi Lee, CIC (Taiwan) # 15.00-15.15 - Coffee Break # 15.15-16.15 - Session 10A : Medea (Toolip) Project Overview Chair person : Dr. Ralf Seepold, Forschungszentrum Informatik (Germany) * "Tools and Methods for IP" Ralf Seepold, FZI (Germany) * "Experiences in Formal Checking of a DSP IP Core" Huy Nam Nguyen, BULL (France) * "A next generation interconnect concept to design high performance SoC's" Carsten Demuth , Infineon (Germany) # 16:15 - Best IP/SOC Design Prize Awards ########## ROOM B: ########## # 08.00-09.40 - Session 6B : Verification and Emulation Chair person : Nuy-nam Nguyen, Bull (France) * "Reusable Verification Infrastructure for a Processor Platform to deliver fast SOC development" Stephen Brain, Glenn Farrall, Infineon Technologies (UK); Kambiz Khalilian, Infineon Technologies (USA) * "Reusability and modularity in SoC Verification environment" Achutha Jois, Vishal Dalal, Sasken communication Technologies Ltd. (India) * "IP "Reuse Hardening" via Embedded Sugar Assertions" Erich Marschner, Grant Martin, Cadence Design Systems (USA) * "The Role of Functional Coverage in Verifying the C166S IP" Andrew Betts, Fabian Delguste, Stephane Brefort, Celia Clause, Qualis (France); Angeles Salas, Thomas Langswert, Infineon * "The SW replicate: Market estimation of a newcoming EDA segment" Marco Pavesi, Italtel (Italy) # 09.40-10.00 - Coffee Break # 10.00-11.40 - Session 7B : Development Tools and Platforms Chair person : Helena Krupnova, ST Microelectronics (France) * "FPGA to ASIC Strategy for Communication SoC Designs" Rick Mosher, AMI Semiconductors (USA) * "Evaluation Strategy for IP Cores Leverages Embedded Linux OS" Yasumasa Nakada, Toshiba Semiconductor Corp. (Japan); Troy Scott, RaveSim Inc. (USA) * "An IP-based SOC Design Kit for Rapid Time-to-Market" Dr Robert Deaves, Dr Andrew Jones, SuperH (UK) * "DAvE - Software based system evaluation in the pre-silicon phase" Timo Bierbaum, Infineon technologies (Germany) * "Object-Oriented Synthesis, Modelling and Partioning for SoC Design" Carsten Schulz-Key, Markus Winterholer, Tommy Kuhn, Wolfgang Rosenstiel, University of Tuebingen (Germany) # 11.40-13.00 - Session 8B : Debugging and Test Chair person : Pierre Bricaud, Synopsys (France) * "Design-for-Test for SoC - Is there a fork in the roadmap?" Ron Press, Mentor Graphics (USA); Richard Illman, Cadence Design Foundry (UK) * "An Embedded Processor Architecture with extensive support for SOC debug" Richard Curnow, SuperH (UK) * "Behavior Analysis for SoC Debugging" Scott Sandler, Yu-Chin Hsu, George Bakewell, Novas Software (USA) * "Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO" Andre Schneider, Karl-Heinz Diener, Gnter Elst - Fraunhofer Institute for Integrated Circuits (Germany); Eero Ivask, Jaan Raik, Raimund Ubar - Tallinn Technical University (Estonia) # 13.00-14.00 - Lunch # 14.00-15.40 - Session 9B : Interconnect and Communication Chair person : Drew Wingard, Sonics (USA) * "Improved Differential form of Transitional Coding" David Craft, IBM (USA) * "Proteo Interconnect IPs for Networks-on-Chip" Ilkka Saastamoinen, Mikko Alho, Juha Pirttimki, Jari Nurmi, Tampere University of Technology (Finland) * "Models for Communication Tradeoffs on Systems-on-Chip" Zeferino Cesar, Kreutz Mrcio, Carro Luigi, Susin Altamiro, UFRGS (Brazil) * "Planning For I/O Interface Development and Integration" Hansel Collins, TriCN (USA) * "Design of communication interface based on configuration for system on chip" Issam MAALEJ, Guy GOGNIAT, Mohamed ABID, Jean Luc PHILIPPE, Ecole Nationale d'Ingenieurs de Sfax (Tunisie); L.E.S.T.E.R., Universit de Bretagne Sud (France) # 15.40-16.45 - Session 10B - Report on the Activities of the VSIA DWG on Virtual Component Quality LOCATION ======== Espace Congres du World Trade Center 7 place Robert Schuman 38025 Grenoble France TRAINING ======== A one-day intensive training organized before the workshop will cover the relevant topics such as IP transfer practices, infrastructure and methodology, as well as IP qualification. See the details of this training program: http://www.us.design-reuse.com/SEMINAR/sem_ip.html ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ AROUND WWW.DESIGN-REUSE.COM ---------------------------- * SPONSOR MESSAGE : Infineon and Synopsys invite you to attend a free seminar. "Fast path to embedded applications with Infineon's proven microcontroller cores and Synopsys DesignWare Star IP". (September 18, 2002 - Santa Clara Marriott Hotel) Click here to register: http://www.us.design-reuse.com/cgi-bin/redirect.pl?ID=168 * SOC NEWS ALERTS Receive free news updates related to the SoC field on your desktop on a regular basis, go to : http://www.us.design-reuse.com/SOCNEWS * D&R ELECTRONIC DESIGN SERVICES MARKETPLACE Post your project for quick access to the best electronic experts, go to : http://www.us.design-reuse.com/DESIGN_SERVICES * MISSED IP BASED DESIGN 2001 ???? The presentations are available online, go to : http://www.us.design-reuse.com/WORKSHOP/ip_design_slides2002.html ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ CHANGE OF ADDRESS/UNSUBSCRIBE ----------------------------- If you need to change the email address at which you receive this newsletter or wish to unsubscribe, you can do it here: http://www.us.design-reuse.com/CONTACT/profile.html and enter your e-mail address as dolinsky@gsu.by ============================================================= DESIGN AND REUSE "The Catalyst of Collaborative SoC Design through IP Exchange" www.design-reuse.com ============================================================= Corporate Headquarters: World Trade Center 5 place Robert Schuman 38025 Grenoble Cedex FRANCE Tel: +33 476 70 64 87 Fax: +33 476 70 64 53 info@design-reuse.com US office: 5600 Mowry School Road Suite 180 Newark, CA 94560 USA Tel: +1 510 656 1445 Fax: +1 510 656 0995 info@design-reuse.com